Second Pass

April 19 2016

The first layout pass exposed some problems with the schematic and I spent a couple days fixing them and improving the design, especially around the power selection. Today's task is to renew the layout and continue.

It appears I lost some of the net class information in the schematic. To avoid hitting this dialog every time I renew the layout from the schematic, I need to update the net classes in the schematic to match the layout.

I created several new nets in the schematic without assigning any class to them.

I renewed the layout. The A3967 circuits didn't change much so that work was preserved.

After about 90 minutes I have a rough draft of the JTAG connection to the 5529. I am using the THERMAL plane for power and ground connections. It is a tight squeeze to the TagConnect pads, even though the connector takes up a huge amount of board space due to the space requirements. The extra space is needed to have room to squeeze the TagConnect hardware to disengage the retaining hooks. And this design has two of them. Once I am confident the ezFET works, I can remove the TagConnect to the 5529.

The power select headers are going to be tricky, since J507:IN1 is connected to the 5528 TagConnect, J507:IN2 is connected to the 5529 TagConnect, and J507:OUT goes to J508 next to the power converter. There will be some long-distance traces involved.

I am replicating the TagConnect and JTAG connections to the 5528, just rotating it by 180°.

My first step after exporting the schematic to layout should have been to group all the components into functional blocks. This is where numbering the components by sheet number pays off. If all the components for the ezFET are near each other, the auto-place and auto-route does a much better job. Trying to sort out the components after the auto-router involves endlessly deleting traces that stretch across the board.